Unless otherwise indicated herein, approaches described in this section are not prior art to the claims listed below and are not admitted as prior art by inclusion in this section.
For digital and mixed-signal integrated circuit (IC) design, such as those of very-large-scale integrated (VLSI) circuits or systems fabricated on one or more monolithic semiconductor substrates, it is imperative that timing requirements or constraints are fulfilled among sequential logic gates such that the circuit or system may function as intended by the design. In general, the timing requirements may include various setup time, hold-time and transition (e.g., slew rate) criteria to be met at either an input or output terminal of sequential logic gates of the IC. In a contemporary IC design flow, the timing requirements are addressed at a later stage of the flow, after the logic gates of the IC are synthesized. A dedicated software tool is usually employed to check whether all timing requirements are met within the IC design. The software tool may further tweak or otherwise fine tune the design to correct any timing violations that are found within the design (i.e., “fix the timing” or “close the timing”).
A conventional approach taken by a timing closure tool or software to fix a hold-time violation is to insert one or more buffers in a data path as delay such that the data may be properly fetched or latched by a sequential-logic device of the IC. This approach, however, is susceptible to various disadvantages, including increased area and leakage power due to the added buffers, as well as potential difficulty of signal routing or rerouting especially in routing congestion areas. In addition, the amount of delay added may be less controlled or predictable due to discrete nature of the buffers and delay variation induced by process, voltage, or temperature (PVT) parameter changes when the IC is fabricated or in operation.
The negative impact to the operation of the IC caused by the disadvantages of the conventional approach stated above can be significant. For example, in a benchmark IC design roughly having 2 million logic instances, it may require a number of close to fifty thousand buffers to be added at the timing fixing stage of the IC design flow to fix the hold-time violations of the IC using the conventional approach, contributing to a 5% increase in silicon area. The accompanying increase of leakage power is also significant. The added leakage power is especially disadvantageous to power sensitive applications such as cellular handsets, tablet computers or other mobile devices.